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ARM Instruction] UBFM, UBFX, UBFIZ, LSR, LSL

UBFM Syntax UBFM Wd, Wn, #, # ; 32-bit general registers UBFM Xd, Xn, #, # ; 64-bit general registers Usage Unsigned Bitfield Move copies any number of low-order bits from a source register into the same number of adjacent bits at any position in the destination register, with zeros in the upper and lower bits. Important! UBFM is an instruction that copies by specifying a memory range and can be..
LLVM-STUDY/BACKEND 2024. 4. 20. 19:40
??????

int test(long long a, long long b, int *table) { return table[(a * b) >> 1]; } clang test(long long, long long, int*): // @test(long long, long long, int*) mul x8, x1, x0 lsl x8, x8, #1 and x8, x8, #0xfffffffffffffffc ldr w0, [x2, x8] ret gcc test(long long, long long, int*): mul x0, x0, x1 asr x0, x0, 1 ldr w0, [x2, x0, lsl 2] ret 버그 lsl x8, x8, #1 1. 최상위 비트가 쉬프트로 인해 손실이 생긴다. 2. 마찬가지로 최하위 비트 (0..
LLVM-STUDY/BACKEND 2024. 4. 17. 06:19
[TODO] Instruction Selection - DAG format 읽기

https://llvm.org/docs/LangRef.html#load-instruction LLVM Language Reference Manual — LLVM 19.0.0git documentation Compiling with ThinLTO causes the building of a compact summary of the module that is emitted into the bitcode. The summary is emitted into the LLVM assembly and identified in syntax by a caret (’^’). The summary is parsed into a bitcode output, along llvm.org 예제] class BaseLoadStore..
LLVM-STUDY/BACKEND 2024. 4. 16. 15:02
[AArch64] Generate stp for complex repeating constansts#514

https://github.com/llvm/llvm-project/issues/51483 [AArch64] Generate stp for complex repeating constansts · Issue #51483 · llvm/llvm-project Bugzilla Link 52141 Version trunk OS Windows NT Reporter LLVM Bugzilla Contributor CC @Arnaud-de-Grandmaison-ARM,@DMG862,@smithp35 Extended Description For complex repeating constants like: void fo... github.com 유사한 최적화 제의와 성능 리포트. https://github.com/dotnet..
LLVM-STUDY/BACKEND 2024. 3. 21. 14:05
Backend 주요 로직 모음

SmallVector WorkList; WorkList.push_back(RetagReg); while (!WorkList.empty()) { Register UseReg = WorkList.pop_back_val(); for (auto &UseI : MRI->use_instructions(UseReg)) { unsigned Opcode = UseI.getOpcode(); if (Opcode == AArch64::STGi || Opcode == AArch64::ST2Gi || Opcode == AArch64::STZGi || Opcode == AArch64::STZ2Gi || Opcode == AArch64::STGPi || Opcode == AArch64::STGloop || Opcode == AArc..
LLVM-STUDY/BACKEND 2024. 3. 19. 01:39
ARM STP instruction

원문 출처 : https://developer.arm.com/documentation/ddi0602/2023-12/Base-Instructions/STP--Store-Pair-of-Registers-?lang=en#iclass_post_index Documentation – Arm Developer developer.arm.com STP 레지스터 쌍 저장은 기본 레지스터 값과 즉시 오프셋에서 주소를 계산하고 두 개의 레지스터에서 계산된 주소에 32비트 단어 2개 또는 64비트 이중 단어 2개를 저장합니다. 메모리 액세스에 대한 자세한 내용은 로드/저장 주소 지정 모드를 참조하세요. It has encodings from 3 classes: Post-index , Pre-index and Signed of..
Study 2024. 3. 18. 21:26
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