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[TODO] Instruction Selection - DAG format 읽기 본문
https://llvm.org/docs/LangRef.html#load-instruction
예제]
class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
string asm, list<dag> pattern>
: I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
bits<5> Rt;
bits<5> Rn;
bits<12> offset;
let Inst{31-30} = sz;
let Inst{29-27} = 0b111;
let Inst{26} = V;
let Inst{25-24} = 0b01;
let Inst{23-22} = opc;
let Inst{21-10} = offset;
let Inst{9-5} = Rn;
let Inst{4-0} = Rt;
let DecoderMethod = "DecodeUnsignedLdStInstruction";
}
multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
Operand indextype, string asm, list<dag> pattern> {
let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
(ins GPR64sp:$Rn, indextype:$offset),
asm, pattern>,
Sched<[WriteLD]>;
def : InstAlias<asm # "\t$Rt, [$Rn]",
(!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
}
defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr",
[(set GPR32z:$Rt,
(load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;
iops | (outs regtype:$Rt) |
oops | (ins GPR64sp:$Rn, indextype:$offset) |
Pattern : 매칭되는 IR ex) %0 = load i32, ptr %arrayidx |
[ (set GPR32z:$Rt, (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset) ) ) ] |
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