[AArch64] LDR (LDRroX, LDRXui)

Load 의 IR 원형
ex) %0 = load i32, ptr %arrayidx

<result> = load [volatile] <ty>, ptr <pointer>
[, align <alignment>][, !nontemporal !<nontemp_node>]
[, !invariant.load !<empty_node>][, !invariant.group !<empty_node>]
[, !nonnull !<empty_node>][, !dereferenceable !<deref_bytes_node>]
[, !dereferenceable_or_null !<deref_bytes_node>][, !align !<align_node>]
[, !noundef !<empty_node>]

 

 

LDR(immediate)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	1	1	1	0	0	0	0	1	0	imm9									0	1	Rn					Rt
size								opc

 

LDRXui (immediate) MIR 예시

renameable $x9 = LDRXui renamable $x0, 3

(outs regtype:$Rt)	(ins GPR64sp:$Rn, indextype:$offset)
renamable $x9 =	LDRXui	renamable $x0	3
Pattern : [(set GPR64z:$Rt, (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]

 

class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
                      string asm, list<dag> pattern>
    : I<oops, iops, asm, "\t$Rt, [$Rn, $offset]", "", pattern> {
  bits<5> Rt;
  bits<5> Rn;
  bits<12> offset;
  let Inst{31-30} = sz;
  let Inst{29-27} = 0b111;
  let Inst{26}    = V;
  let Inst{25-24} = 0b01;
  let Inst{23-22} = opc;
  let Inst{21-10} = offset;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rt;

  let DecoderMethod = "DecodeUnsignedLdStInstruction";
}

 

multiclass LoadUI<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
                  Operand indextype, string asm, list<dag> pattern> {
  let AddedComplexity = 10, mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
  def ui : BaseLoadStoreUI<sz, V, opc, (outs regtype:$Rt),
                           (ins GPR64sp:$Rn, indextype:$offset),
                           asm, pattern>,
           Sched<[WriteLD]>;

  def : InstAlias<asm # "\t$Rt, [$Rn]",
                  (!cast<Instruction>(NAME # "ui") regtype:$Rt, GPR64sp:$Rn, 0)>;
}

 

 

 

defm LDRW : LoadUI<0b10, 0, 0b01, GPR32z, uimm12s4, "ldr",
                   [(set GPR32z:$Rt,
                         (load (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)))]>;

defm LDRX : LoadUI<0b11, 0, 0b01, GPR64z, uimm12s8, "ldr",
                   [(set GPR64z:$Rt,
                         (load (am_indexed64 GPR64sp:$Rn, uimm12s8:$offset)))]>;

 

iops	(outs regtype:$Rt)
oops	(ins GPR64sp:$Rn, indextype:$offset)
Pattern : 매칭되는 IR ex) %0 = load i32, ptr %arrayidx	[ (set GPR32z:$Rt,   (load     (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)   ) ) ]

 

 

 

LDR (register)

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
1	x	1	1	1	0	0	0	0	1	1	Rm					option			S	1	0	Rn					Rt
size								opc

 

LDRXroW MIR 예시

renamable $x8 = LDRXroW killed renamable $x8, killed renamable $w2, 1, 1

(outs regtype:$Rt)	(ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)
renamable $x8 =	LDRXroW	killed renamable $x8	killed renamable $w2	1, 1
Pattern : [(set (Ty regtype:$Rt), (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)))]

 

 

class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, string asm, dag ins,
                    dag outs, list<dag> pat>
    : I<ins, outs, asm, "\t$Rt, [$Rn, $Rm, $extend]", "", pat> {
  bits<5> Rt;
  bits<5> Rn;
  bits<5> Rm;
  bits<2> extend;
  let Inst{31-30} = sz;
  let Inst{29-27} = 0b111;
  let Inst{26}    = V;
  let Inst{25-24} = 0b00;
  let Inst{23-22} = opc;
  let Inst{21}    = 1;
  let Inst{20-16} = Rm;
  let Inst{15}    = extend{1}; // sign extend Rm?
  let Inst{14}    = 1;
  let Inst{12}    = extend{0}; // do shift?
  let Inst{11-10} = 0b10;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rt;
}

 

multiclass Load32RO<bits<2> sz, bit V, bits<2> opc, DAGOperand regtype,
                    string asm, ValueType Ty, SDPatternOperator loadop> {
  let AddedComplexity = 10 in
  def roW : LoadStore32RO<sz, V, opc, asm, (outs regtype:$Rt),
                 (ins GPR64sp:$Rn, GPR32:$Rm, ro_Wextend32:$extend),
                 [(set (Ty regtype:$Rt),
                       (loadop (ro_Windexed32 GPR64sp:$Rn, GPR32:$Rm,
                                              ro_Wextend32:$extend)))]>,
           Sched<[WriteLDIdx, ReadAdrBase]> {
    let Inst{13} = 0b0;
  }

  let AddedComplexity = 10 in
  def roX : LoadStore32RO<sz, V, opc, asm, (outs regtype:$Rt),
                 (ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend),
                 [(set (Ty regtype:$Rt),
                       (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,
                                              ro_Xextend32:$extend)))]>,
           Sched<[WriteLDIdx, ReadAdrBase]> {
    let Inst{13} = 0b1;
  }

  def : ROInstAlias<asm, regtype, !cast<Instruction>(NAME # "roX")>;
}

 

defm LDRW  : Load32RO<0b10, 0, 0b01, GPR32, "ldr", i32, load>;
defm LDRX  : Load64RO<0b11, 0, 0b01, GPR64, "ldr", i64, load>;

 

iops	(ins GPR64sp:$Rn, GPR64:$Rm, ro_Xextend32:$extend)
oops	(outs regtype:$Rt)
Pattern : 매칭되는 IR ex) %0 = load i32, ptr %arrayidx	[(set (Ty regtype:$Rt),                        (loadop (ro_Xindexed32 GPR64sp:$Rn, GPR64:$Rm,                                               ro_Xextend32:$extend)))]