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목록LLVM-STUDY/MIR (4)
Why should I know this?
https://archive.fosdem.org/2019/schedule/event/llvm_tablegen/attachments/slides/3304/export/events/attachments/llvm_tablegen/slides/3304/tablegen.pdf
Store IR 원형store [volatile] , ptr [, align ][, !nontemporal !][, !invariant.group !]; yields voidstore atomic [volatile] , ptr [syncscope("")] , align [, !invariant.group !] ; yields void! = !{ i32 1 }! = !{}STRroX, STRroWSTR(register) 3130292827262524232221201918171615141312111098765432101x111000001RmoptionS10RnRtsize opc STRroX, STRroW 예시str x0, [x9, x8, lsl #3]storeopTy regtype:$..
Load 의 IR 원형 ex) %0 = load i32, ptr %arrayidx = load [volatile] , ptr [, align ][, !nontemporal !][, !invariant.load !][, !invariant.group !][, !nonnull !][, !dereferenceable !][, !dereferenceable_or_null !][, !align !][, !noundef !] LDR(immediate)3130292827262524232221201918171615141312111098765432101x111000010imm901RnRtsize opc LDRXui (immediate) MIR 예시renameable $x9 = LDRXui renamable $x..
원문 출처 : https://developer.arm.com/documentation/ddi0602/2023-12/Base-Instructions/STP--Store-Pair-of-Registers-?lang=en#iclass_post_index Documentation – Arm Developer developer.arm.com // FIXME: Use dedicated range-checked addressing mode operand here.defm STPW : StorePairOffset;defm STPX : StorePairOffset; multiclass StorePairOffset opc, bit V, RegisterOperand regtype, ..